Semiconductor Engineer in Santa Clara, CA

Job Title: Principal Advanced Packaging Engineer Semiconductor & Chiplet Integration Location: Santa Clara, CA Visas: and H1b Industry: Semiconductor | Microelectronics | Advanced Packaging Experience Level: Senior (10+ Years) ________________________________________ Position Summary We are seeking an experienced Principal Advanced Packaging Engineer with deep expertise in semiconductor packaging, chiplet integration, and high-speed interconnect design. This role will lead advanced packaging development efforts for next-generation AI, HPC, and communication systems. You will work on 2.5D/3D integration, BEOL process optimization, and substrate innovation, driving solutions from concept to production in a highly collaborative, cross-functional environment. ________________________________________ Key Responsibilities Design and develop advanced IC packaging architectures including flip-chip, TSV, 2.5D/3D stacking, and chiplet integration for AI and HPC applications. Lead substrate development including organic, silicon, and glass interposers to optimize power/signal integrity and thermal performance. Collaborate with ASIC, foundry, and OSAT teams to ensure seamless integration across BEOL, substrate, and package levels. Implement and evaluate advanced interconnect technologies using Cadence, ANSYS, Siemens NX, and other EDA tools. Drive package-level simulations for thermal, mechanical, and electrical reliability. Support quality, reliability, and failure analysis programs using SEM, TEM, FIB, AFM, and Raman spectroscopy. Utilize FMEA, SPC, and DOE to optimize process development and ensure first-time-right product builds. Mentor junior engineers and contribute to technical training programs focused on advanced packaging and chiplet integration. ________________________________________ Required Qualifications Master s degree in Materials Science, Electrical Engineering, or related discipline. 10+ years of experience in semiconductor packaging, with focus on chiplet and heterogeneous integration. Proven expertise in high-speed I/O design, substrate development, and BEOL/FEOL integration. Hands-on experience with Siemens NX, Cadence Allegro/Virtuoso, ANSYS, JMP, and ThermoCalc. Proficiency in reliability testing and metrology including SEM, TEM, AFM, XPS. Deep understanding of package-related failure modes and root cause analysis. Familiarity with AI and HPC-specific packaging challenges and opportunities. ________________________________________ Preferred Qualifications Manufacturing certification. Experience with PIC/EIC packaging or wafer-level integration. System-level understanding of AR/VR, RF, or space-grade electronics. Cross-disciplinary experience in academia, R&D, and high-volume manufacturing Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity. Report this job

• Dice Id: 10204403
• Position Id: 8624429