Design Verification Engineer

Design Verification – 6+ Years Experience – H1B Job RequirementsLocation: San Jose, CA, USAPOSITION: Senior DV Engineer


Role SummaryThe Senior Engineer – DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high qualit y.Key Responsibiliti

• esDesign Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express et
• c.Strong in HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flow
• s.Strong in constraint random verification, assertion writing, coverage analysis, debuggin
• g.Familiarity with ARM cores, formal verification, SV DPI-C is a plu
• s.Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plu
• s.Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plu
• s.Must be a team player with good oral and written communication skill
• s.Self-motivated with the ability to work independently and interface effectively with engineers across divisions and remote location

s.EducationBE / BTech / MTech in Electronics, Electrical, or related discipline s.Work Requirement:This role is considered an on-site position located in San Jose / Irvine / San Dieag

• o.You must be able to commute to and from the location with your own transportation arrangements to meet the required working hour

s.