Design Verification Engineer

Functional verification of complex designs.
Responsible for verification from test planning, test bench development, test execution and functional/code coverage closure.
Skills/Expertise:
Expertise in architecting reusable and constrained random test benches from scratch. Expertise in verification methodologies like UVM.
Verification expertise with Interface IP designs. Beneficial areas would include High bandwidth memory (HBM) PHY / controller sub-systems, Ethernet/PCIE/CXL (Physical coding sublayer)/Serdes designs.
Experience with ARM based bus protocols like APB, AXI and CHI is highly desirable. Strong understanding of System Verilog assertions and ability to quickly write effective coverage and assertion properties.

Minimum Industry Experience : Bachelor's Degree + 8+ years of related experience; OR Master's Degree + 6+ years of experience.
Having Exp in Memory Controllers And Or HBM or Ethernet/MAC is also a PLUS.
* H1B Transfer IS NOT open at this time.