Location: Austin, TX (On-site, 5 days/week)
Employment Type: Full-time
Salary: USD 150,000 – 200,000 per year + Equity (4-year vesting)
Relocation Assistance: Available (case-by-case)
Visa Sponsorship: H1-B sponsorship available
About the Role We’re looking for a
Senior Algorithm Engineer specializing in
Error Correction Codes (ECC) to join an advanced
R&D team developing
next-generation coherent optical transceivers for
Data Center Interconnects (DCI) at
800Gbps and
1600Gbps.
You’ll play a key role in
designing, simulating, and optimizing ECC algorithms while collaborating with cross-functional teams, including
Systems, VLSI, Design Verification, and Firmware.
Key Responsibilities- Design & Simulate ECC Architectures – Define performance requirements and drive specifications for digital and firmware designers.
- Develop & Integrate ECC Algorithms – Build and simulate ECC models and integrate them with MODEM simulations.
- Cross-functional Collaboration – Partner with designers to ensure efficient implementation and participate in bring-up, validation, and optimization activities.
- Hands-on Development – Translate high-level MATLAB models into hardware-friendly architectures.
Requirements- 5+ years of hands-on experience developing ECC algorithms with a proven track record.
- Expertise in MATLAB and C for fixed-point design and programming.
- Deep understanding of system constraints and hardware implementation (MATLAB-to-RTL flow).
- Lab experience with debugging and tuning algorithms.
Preferred Skills- Experience in optical communications is a strong advantage.
- Familiarity with coherent DSP architectures or high-speed optical networking is a plus.
Additional Details- Office Location: Austin, TX
- Interview Process: 3 rounds, typically completed within 2 weeks.
- Equity: Offered with a 4-year vesting schedule.
- Relocation Expenses: Considered on a case-by-case basis.