Hiring: ASIC Design Engineer | Austin, TX (On-Site)Full-Time | Permanent | Full Medical & Dental | Relocation: YesAccepting: USC/GC Holder/H1BWe’re looking for an experienced ASIC Design Engineer / Micro-Architect to help build next-gen communication systems from the ground up. This is a hands-on, on-site role in Austin, TX (5 days/week). What You’ll Do
Translate high-level algorithms into efficient RTL hardware architectures
Define micro-architecture and write RTL (Verilog / SystemVerilog / VHDL)
Work closely with Verification, DFT (ATPG, BIST), and Physical Design teams
Perform synthesis, timing analysis, and debug (pre/post-silicon)
Optimize for Power, Performance & Area (PPA)
Support IP/SoC integration and documentation
Must-Have Skills
5+ years as ASIC/FPGA RTL Designer
Strong Verilog/SystemVerilog skills
Solid RTL, synthesis, and timing analysis experience
Understanding of DFT (scan, ATPG, BIST)
Experience working with simulation & verification environments
BS/MS in EE/CE
Must be willing to work on-site in Austin, TX
Nice to Have
Optical Communication or DSP experience
High-speed Ethernet (100G+)
Python/Perl/TCL scripting
Low-power or CDC/Voltage domain crossing experience