ator specializing in programmable coherent DSP (Digital Signal Processing) solutions for cloud and AI infrastructure seeks a DSP Algorithms Engineer (System C Simulation) to join their Optical DSP team in Austin, Texas.
The company has secured over $180 million in funding from elite investors including Kleiner Perkins, Spark Capital, Mayfield, and Fidelity Investments, and is building next-generation DSP technologies enabling ultra-fast data transmission between AI data centers.
This role offers the opportunity to work at the intersection of optical systems, DSP algorithms, and System C simulation, directly contributing to the architecture and performance of coherent optical DSP ASICs.
Key Responsibilities
Develop a comprehensive System C simulation platform that models full optical DSP systems, including TX/RX data paths, analog front-end, optical subassemblies, and firmware interaction.
Translate MATLAB-based DSP models into efficient System C/C++ implementations.
Design and integrate simulation frameworks for timing recovery, equalization, carrier recovery, FEC, DAC/ADC, and optical channel modeling.
Model real-world effects such as fiber impairments, noise, jitter, and OSNR to evaluate DSP performance (BER, EVM, sensitivity).
Collaborate closely with DSP algorithm developers, ASIC design, and verification teams to ensure seamless architecture validation.
Build regression test environments and ensure robust verification of full DSP chains.
Document simulation architectures, APIs, and development methodologies for team-wide usage.
Support architecture trade-off studies and provide insights that influence DSP ASIC design decisions.
Must-Have Qualifications
Master’s degree (MSc) in Electrical Engineering, Computer Engineering, or a related field.
Minimum 10 years of experience in DSP design and modeling for communications, optical, or related systems.
Strong proficiency in System C / C++, with proven experience building modular simulation environments.
Hands-on experience with MATLAB DSP prototyping and translation into System C.
Solid understanding of digital communication systems:
Modulation
Equalization
Coding
Carrier & timing recovery
Familiarity with coherent optical communications and fixed-point modeling.
Experience in DSP ASIC design flow and cross-functional collaboration with hardware/firmware teams.
Excellent analytical, debugging, and teamwork skills.
Job stability and continuity — no frequent job changes or breaks.
Nice-to-Have Qualifications
Experience with verification methodologies such as UVM/SystemVerilog or HW/SW co-simulation.
Familiarity with HDLs (VHDL/Verilog) or HLS (High-Level Synthesis) design flows.
Exposure to FEC algorithms (LDPC, RS, OFEC) and their integration in DSP systems.
Understanding of PLL/CDR, jitter modeling, and mixed-signal impairments in high-speed systems.
Experience in ASIC system-level performance validation or optical link modeling.