Packaging Designer

Principal Or Senior Package design Engineer:
Locations Austin Or Fort Collins OR San Jose:
H1B supported: ( with i-140 approved)
Package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. Developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. RESPONSIBILITIES: ·Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. ·1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest (3 or more years is preferred) · Package Design of critical structures for SerDes, ADC/DAC, DDR, etc. · Schedule, prioritize, & track your work across 2+ projects simultaneously · General flip-chip BGA package design & engineering · Project management and customer interface for your design projects EDUCATION/EXPERIENCE & REQUIREMENTS: · Experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes ·Knowledge of package-level signal integrity and power integrity, to apply to package designs ·Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.