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VLSI RTL Design Engineer – ASIC/FPGA Development

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VLSI RTL Design Engineer – ASIC/FPGA Development
Mogi IO OTTPodcastShort Video Apps for you
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Austin, Texas, United States
Classification symbol Engineering
H-1B
Salary
150000 - 200000 USD /YEAR
Job posted on September 3, 2025
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Job Description:
Work Type: Full-Time | Permanent | Onsite – Austin, TX (5 days a week)

Experience Required: 5–10 Years (ASIC/FPGA Design, RTL Development)

Compensation: USD $150,000 – $200,000 + Equity (4-year vesting)

Industry/Domain: Semiconductor / Cloud & AI Infrastructure / DSP Solutions

Job Overview

We are seeking talented and experienced VLSI RTL Designers / Micro-Architects to join a fast-growing semiconductor innovator in Austin. In this role, you will design highly sophisticated communication systems from the ground up, contributing to next-generation DSP (digital signal processing) solutions that power AI and cloud data center connectivity.

Key Responsibilities
  • Translate high-level algorithmic requirements into efficient hardware implementations.
  • Interpret and apply protocol specifications (e.g., Ethernet 100G+).
  • Drive all design stages: micro-architecture definition, RTL coding (Verilog/SystemVerilog/VHDL), synthesis-friendly coding, timing-aware design.
  • Collaborate cross-functionally with:
    • Verification teams – testbench development, debug, coverage closure.
    • DFT teams – scan insertion, ATPG, BIST integration.
    • Physical design teams – floorplanning, timing closure, routing feedback.
  • Perform synthesis and timing analysis, generate SDC constraints, and debug functional/timing issues.
  • Optimize RTL for area, power, and performance (PPA).
  • Maintain detailed design documentation (micro-architecture specs, interface docs).
  • Contribute to IP/SoC integration and handle system-level interfaces.
  • Support silicon bring-up and validation (preferred).
  • Stay updated on EDA tools, CDC, linting, and formal verification methodologies.

Must-Have Skills & Qualifications

  • Minimum 5 years of experience in ASIC/FPGA design.
  • Strong Verilog/SystemVerilog expertise.
  • Proficiency in simulation tools, verification methodologies.
  • Strong teamwork, interpersonal, and problem-solving skills.
  • BS/MS in EE/CE from a leading institution.
  • Willingness to work on-site in Austin, TX, five days a week.

Preferred Skills & Attributes
  • Background in:
    • Clock/Voltage domain crossing, Low Power Design, DFT.
    • DSP-oriented design blocks.
    • Ethernet (100G and above).
  • Scripting experience in Python, Perl, TCL.
  • Experience with optical communication systems (a plus).

Additional Information

  • Visa: Open to sponsor H1-B.
  • Medical & Dental: Full coverage.
  • Relocation Expenses: Case-by-case basis.

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